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? 1996 mos integrated circuit MC-428LFF721 3.3 v operation 8m-word by 72-bit dynamic ram module unbuffered type, edo data sheet the mark ? ? shows major revised points. document no. m11912ej3v0ds00 (3rd edition) date published october 1997 ns printed in japan the information in this document is subject to change without notice. description the MC-428LFF721 is a 8,388,608 words by 72 bits dynamic ram module on which 9 pieces of 64m dram : m pd4264805 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? unbuffered type ? edo (hyper page mode) ? 8,388,608 words by 72 bits organization ? fast access and cycle time family access time r/w c y cle time edo (h y per pa g e mode) power consumption (max.) (max.) (min.) cycle time (min.) active standby MC-428LFF721-a50 50 ns 84 ns 20 ns 3.40 w 16.2 mw MC-428LFF721-a60 60 ns 104 ns 25 ns 3.08 w (cmos level input) ? refresh cycle family refresh cycle refresh MC-428LFF721-a50 8,192 cycles / 64 ms /ras only refresh, normal read / write MC-428LFF721-a60 4,096 cycles / 64 ms /cas before /ras refresh, hidden refresh ? 168-pin dual in-line memory module (pin pitch = 1.27 mm) ? single +3.3 v 0.3 v power supply ? serial pd
2 MC-428LFF721 ordering information part number access time (max.) package mounted devices MC-428LFF721fh-a50 50 ns 168-pin dual in-line memory module (socket type) 9 pieces of m pd4264805g5 (400 mil tsop(ii)) MC-428LFF721fh-a60 60 ns edge connector : gold plated [single side] MC-428LFF721fb-a50 50 ns 9 pieces of m pd4264805le (400 mil soj) MC-428LFF721fb-a60 60 ns [single side]
3 MC-428LFF721 pin configuration 168-pin dual in-line memory module socket type (edge connector: gold plated) [ MC-428LFF721fh, 428lff721fb ] 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 gnd dq 32 dq 33 dq 34 dq 35 vcc dq 36 dq 37 dq 38 dq 39 dq 40 gnd dq 41 dq 42 dq 43 dq 44 dq 45 vcc dq 46 dq 47 cb4 cb5 gnd nc nc vcc nc /cas4 /cas5 nc nc gnd a1 a3 a5 a7 a9 a11 nc vcc nc nc gnd nc nc /cas6 /cas7 nc vcc nc nc cb6 cb7 gnd dq 48 dq 49 dq 50 dq 51 vcc dq 52 nc nc nc gnd dq 53 dq 54 dq 55 gnd dq 56 dq 57 dq 58 dq 59 vcc dq 60 dq 61 dq 62 dq 63 gnd nc nc sa0 sa1 sa2 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 gnd dq 0 dq 1 dq 2 dq 3 vcc dq 4 dq 5 dq 6 dq 7 dq 8 gnd dq 9 dq 10 dq 11 dq 12 dq 13 vcc dq 14 dq 15 cb0 cb1 gnd nc nc vcc /we0 /cas0 /cas1 /ras0 /oe0 gnd a0 a2 a4 a6 a8 a10 a12 vcc vcc nc gnd /oe2 /ras2 /cas2 /cas3 /we2 vcc nc nc cb2 cb3 gnd dq 16 dq 17 dq 18 dq 19 vcc dq 20 nc nc nc gnd dq 21 dq 22 dq 23 gnd dq 24 dq 25 dq 26 dq 27 vcc dq 28 dq 29 dq 30 dq 31 gnd nc nc nc sda scl vcc a0 - a12 : address inputs [ row : a0 - a12, column : a0 - a9 ] dq0 - dq63 : data inputs / outputs / ras0, /ras2 : row address strobe / cas0 - /cas7 : column address strobe / we0, /we2 : write enable / oe0, /oe2 : output enable sda : serial data i/o for pd scl : clock input for pd sa0 - sa2 : address input for eeprom cb0 - cb7 : check bits v cc : power supply gnd : ground nc : no connection / xxx indicates active low si gnal.
4 MC-428LFF721 block diagram remark d0 - d8 : m pd4264805 (8m words by 8 bits organization) /cas0 /we0 /oe0 /ras0 /cas4 /we2 /oe2 /ras2 /cas d0 /ras /we /oe dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 d1 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 d2 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 d3 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 d4 d7 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 d8 d6 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 d5 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 cb 0 cb 1 cb 2 cb 3 cb 4 cb 5 cb 6 cb 7 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 a0 - a12 a0 - a12 : d0 - d8 v cc d0 - d8 gnd d0 - d8 serial pd scl sda a0 a1 a2 sa0 sa1 sa2 /cas1 / cas2 / cas3 / cas7 /cas6 /cas5 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe /cas/ras /we /oe dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7
5 MC-428LFF721 electrical specifications ? all voltages are referenced to gnd. ? after power up (v cc 3 v cc (min.) ), wait more than 100 m s (/ras, /cas inactive) and then, execute eight /cas before /ras or /ras only refresh cycles as dummy cycles to initialize internal circuit. absolute maximum ratings parameter symbol condition rating unit voltage on any pin relative to gnd v t - 0.5 to +4.6 v supply voltage v cc - 0.5 to +4.6 v output current i o 50 ma power dissipation p d 9w operating ambient temperature t a 0 to +70 c storage temperature t stg - 55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il - 0.3 +0.8 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a12 90 pf c i2 /ras0, /ras2 50 c i3 /cas0 - /cas7 35 c i4 /we0, /we2 50 c i5 /oe0, /oe2 50 data input / output capacitance c i/o dq0 - dq63, cb0 - cb7 30 pf
6 MC-428LFF721 dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 /ras, /cas cycling t rac = 50 ns 945 ma 1, 2, 3 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 855 standby current i cc2 /ras, /cas 3 v ih (min.) , i o = 0 ma 9.0 ma /ras, /cas 3 v cc - 0.2 v, i o = 0 ma 4.5 /ras only refresh current i cc3 /ras cycling, /cas 3 v ih (min.) t rac = 50 ns 945 ma 1, 2, 3 ,4 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 855 operating current i cc4 /ras v il (max.) , /cas cycling t rac = 50 ns 945 ma 1, 2, 5 (hyper page mode (edo)) t hpc = t hpc (min.) , i o = 0 ma t rac = 60 ns 855 /cas before /ras i cc5 /ras cycling t rac = 50 ns 1,215 ma 1, 2 refresh current t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 1,035 input leakage current i i (l) v i = 0 to 3.6 v - 5+5 m a all other pins not under test = 0 v output leakage current i o (l) v o = 0 to 3.6 v - 5+5 m a output is disabled (hi - z) high level output voltage v oh i o = - 2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v notes 1. i cc1 , i cc3 , i cc4 and i cc5 depend on cycle rates (t rc and t hpc ). 2. specified values are obtained with outputs unloaded. 3. i cc1 and i cc3 are measured assuming that address can be changed once or less during /ras v il (max.) and /cas 3 v ih (min.) . 4. i cc3 is measured assuming that all column address inputs are held at either high or low. 5. i cc4 is measured assuming that all column address inputs are switched only once during each hyper page (edo) cycle.
7 MC-428LFF721 ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions (1) input timing specification (2) output timing specification (3) output load condition v il (max.) = 0.8 v v ih (min.) = 2.0 v v oh (min.) = 2.0 v v ol (max.) = 0.8 v t t = 2 ns t t = 2 ns i/o 870 100 pf 1,180 v cc c l
8 MC-428LFF721 common to read, write, read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t rc 84 - 104 - ns /ras precharge time t rp 30 - 40 - ns /cas precharge time t cpn 7 - 10 - ns /ras pulse width t ras 50 10,000 60 10,000 ns /cas pulse width t cas 8 10,000 10 10,000 ns /ras hold time t rsh 13 - 15 - ns /cas hold time t csh 38 - 40 - ns /ras to /cas delay time t rcd 11 37 14 45 ns 1 /ras to column address delay time t rad 9251230 ns 1 /cas to /ras precharge time t crp 5 - 5 - ns 2 row address setup time t asr 0 - 0 - ns row address hold time t rah 7 - 10 - ns column address setup time t asc 0 - 0 - ns column address hold time t cah 7 - 10 - ns /oe lead time referenced to /ras t oes 0 - 0 - ns /cas to data setup time t clz 0 - 0 - ns /oe to data setup time t olz 0 - 0 - ns /oe to data delay time t oed 10 - 13 - ns transition time (rise and fall) t t 150150 ns refresh time t ref - 64 - 64 ms notes 1. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. t crp (min.) requirement is applied to /ras, /cas cycles.
9 MC-428LFF721 read cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. access time from /ras t rac - 50 - 60 ns 1 access time from /cas t cac - 13 - 15 ns 1 access time from column address t aa - 25 - 30 ns 1 access time from /oe t oea - 13 - 15 ns column address lead time referenced to /ras t ral 25 - 30 - ns read command setup time t rcs 0 - 0 - ns read command hold time referenced to /ras t rrh 0 - 0 - ns 2 read command hold time referenced to /cas t rch 0 - 0 - ns 2 output buffer turn-off delay time from /oe t oez 010013 ns 3 /cas hold time to /oe t cho 5 - 5 - ns 4 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. either t rch (min.) or t rrh (min.) should be met in read cycles. 3. t oez (max.) defines the time when the output achieves the condition of hi-z and is not referenced to v oh or v ol . 4. /we : inactive (in read cycle) /cas : inactive, /oe : active ...... t cho is effective. /ras, /oe : active ...... t och is effective.
10 MC-428LFF721 write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. /we hold time referenced to /cas t wch 7 - 10 - ns 1 /we pulse width t wp 7 - 10 - ns 1 /we lead time referenced to /ras t rwl 13 - 15 - ns /we lead time referenced to /cas t cwl 7 - 10 - ns /we setup time t wcs 0 - 0 - ns 2 /oe hold time t oeh 0 - 0 - ns data-in setup time t ds 0 - 0 - ns 3 data-in hold time t dh 7 - 10 - ns 3 notes 1. t wp (min.) is applied to late write cycles or read modify write cycles. in early write cycles, t wch (min.) should be met. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. 3. t ds (min.) and t dh (min.) are referenced to the /cas falling edge in early write cycles. in late write cycles and read modify write cycles, they are referenced to the /we falling edge. read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. read modify write cycle time t rwc 107 - 133 - ns /ras to /we delay time t rwd 64 - 77 - ns 1 /cas to /we delay time t cwd 27 - 32 - ns 1 column address to /we delay time t awd 39 - 47 - ns 1 note 1. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate.
11 MC-428LFF721 hyper page mode (edo) parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t hpc 20 - 25 - ns 1 /ras pulse width t rasp 50 125,000 60 125,000 ns /cas pulse width t hcas 8 10,000 10 10,000 ns /cas precharge time t cp 7 - 10 - ns access time from /cas precharge t acp - 30 - 35 ns /cas precharge to /we delay time t cpwd 41 - 52 - ns 2 /ras hold time from /cas precharge t rhcp 30 - 35 - ns read modify write cycle time t hprwc 52 - 66 - ns data output hold time t dhc 5 - 5 - ns /oe to /cas hold time t och 5 - 5 - ns 3 /oe precharge time t oep 5 - 5 - ns output buffer turn-off delay from /we t wez 010013 ns 4,5 /we pulse width t wpz 7 - 10 - ns 5 output buffer turn-off delay from /ras t ofr 010013 ns 4,5 output buffer turn-off delay from /cas t ofc 010013 ns 4,5 notes 1. t hpc (min.) is applied to /cas access. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. 3. /we : inactive (in read cycle) /cas : inactive, /oe : active ...... t cho is effective. /cas, /oe : active ...... t och is effective. 4. t ofc (max.) , t ofr (max.) and t wez (max.) define the time when the output achieves the conditions of hi-z and is not referenced to v oh or v ol . 5. to make dqs to hi-z in read cycle, it is necessary to control /ras, /cas, /we, /oe as follows. the effective specification depends on state of each signal. (1) both /ras and /cas are inactive (at the end of the read cycle) /we : inactive, /oe : active t ofc is effective when /ras is inactivated before /cas is inactivated. t ofr is effective when /cas is inactivated before /ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both /ras and /cas are active or either /ras or /cas is active (in read cycle) /we, /oe : inactive ...... t oez is effective. both /ras and /cas are inactive or /ras is active and /cas is inactive (at the end of read cycle) /we, /oe : active and either t rrh or t rch must be met ...... t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective.
12 MC-428LFF721 refresh cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. /cas setup time t csr 5 - 5 - ns /cas hold time (/cas before /ras refresh) t chr 10 - 10 - ns /ras precharge /cas hold time t rpc 5 - 5 - ns /we setup time t wsr 10 - 10 - ns /we hold time t whr 15 - 15 - ns
13 MC-428LFF721 serial pd byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 number of serial pd bytes 5dh 0 1 0 1 1 1 0 1 93 bytes 1 serial memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 02h 0 0 0 0 0 0 1 0 edo 3 number of rows 0dh 0 0 0 0 1 1 0 1 13 rows 4 number of columns 0ah 0 0 0 0 1 0 1 0 10 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 48h 0 1 0 0 1 0 0 0 72 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 /ras access time -a50 32h 0 0 1 1 0 0 1 0 50 ns -a60 3ch 0 0 1 1 1 1 0 0 60 ns 10 /cas access time -a50 0dh 0 0 0 0 1 1 0 1 13 ns -a60 0fh 0 0 0 0 1 1 1 1 15 ns 11 error detection/correction 02h 0 0 0 0 0 0 1 0 ecc 12 refresh period 00h 0 0 0 0 0 0 0 0 normal 13dram width 08h00001000 8 14 error checking dram width 08h 0 0 0 0 1 0 0 0 8 15 - 61 00h 0 0 0 0 0 0 0 0 none 62spd revision 01h000000011 63 checksum for bytes 0 - 62 -a50 1ah 0 0 0 1 1 0 1 0 -a6026h00100110 64 manufactures jedec id code per jep-106e 10h00010000 65-71 00h 0 0 0 0 0 0 0 0 72 manufacturing location 73 part name 34h 0 0 1 1 0 1 0 0 74 part name 32h 0 0 1 1 0 0 1 0 75 part name 38h 0 0 1 1 1 0 0 0 76part name 4ch01001100 77 part name 46h 0 1 0 0 0 1 1 0 78 part name 46h 0 1 0 0 0 1 1 0 79 part name 37h 0 0 1 1 0 1 1 1 80 part name 32h 0 0 1 1 0 0 1 0 81 part name 31h 0 0 1 1 0 0 0 1 82 part name 46h 0 1 0 0 0 1 1 0 83 part name MC-428LFF721fb 42h 0 1 0 0 0 0 1 0 MC-428LFF721fh 48h 0 1 0 0 1 0 0 0 84part name 2dh00101101 85 part name 41h 0 1 0 0 0 0 0 1 86 part name -a50 35h 0 0 1 1 0 1 0 1 -a6036h00110110 87 part name 30h 0 0 1 1 0 0 0 0 88 part name 20h 0 0 1 0 0 0 0 0 89 part name 20h 0 0 1 0 0 0 0 0 90 part name 20h 0 0 1 0 0 0 0 0 91 pcb revision code 31h 0 0 1 1 0 0 0 1 92 blank 20h 0 0 1 0 0 0 0 0 remark 1 : high level (serial data), 0 : low level (serial data)
14 MC-428LFF721 read cycle data out hi - z v ih v il /cas v ih v il /ras v ih v il address v ih v il /we v oh v ol dq v ih v il /oe crp t rcd t csh t ras t rc t rsh t cas t ral t cah t asc t col. rcs t och t oes t oea t clz t olz t cac t aa t rac t rp t cpn t rch t rrh t wpz t cho t wez t ofc t oez t ofr t hi - z asr t rah t rad t row
15 MC-428LFF721 early write cycle ds t crp t rcd t wch t wcs t asr t rah t rad t asc t cah t cas t rsh t csh t ras t rp t rc t v ih v il v ih v il v ih v il v ih v il v ih v il /ras address /we row col. data in dh t cpn t /cas dq remark /oe : dont care
16 MC-428LFF721 late write cycle /ras address /we row col. data in /oe hi - z rc t rp t ras t crp t rcd t cas t rsh t csh t cpn t asr t rah t rad t asc t cah t wp t rwl t cwl t rcs t oeh t oed t ds t dh t v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il /cas dq
17 MC-428LFF721 read modify write cycle /ras /cas address /we dq /oe dq row col. data in hi - z data out hi - z v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il rwc t ras t rp t cpn t rsh t cas t csh t rcd t crp t asr t rah t rad t cah t asc t rcs t oea t oeh t ds t dh t oed t aa t rac t cac t clz t olz t oez t cwl t rwl t wp t rwd t awd t cwd t
18 MC-428LFF721 hyper page mode (edo) read cycle /ras /cas address /we /oe dq t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t rad t cah t asc t cah t asc t cah t ral t rcs t rch t rrh t wpz t wez t oez t acp t aa t cac t acp t aa t cac t dhc t dhc t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z t ofr t ofc t och v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il cho t t asc remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
19 MC-428LFF721 hyper page mode (edo) read cycle (/we control) /ras /cas address /we /oe t rasp t rp t crp t rcd t hcas t csh t rhcp t rsh t hcas t cpn t hcas t asr t rah t rad t cah t asc t cah t asc t cah t ral t rrh t wpz t ofr t ofc t oez t aa t aa t clz t cac t cac t clz t wez t wez t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z dq t rch t wpz t rcs t rch t wpz t rcs t rch hi - z hi - z t wez t och v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il cho t t asc t rcs remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
20 MC-428LFF721 hyper page mode (edo) read cycle (/oe control) hi - z hi - z row col.a col.b col.c /ras /cas address /oe dq data out a data out c /we v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il rasp t rp t rhcp t cpn t rsh t hcas t cp t hpc t hcas t cp t hcas t csh t rcd t crp t rad t rah t asr t asc t cah t cah t asc t cah t ral t ofr t ofc t rrh t rch t oes t aa t cac t cac t aa t rac t rcs t oep t t och t oea t cho t acp t och t oep t cho t oep t aa t cac t acp t och t cho t oez t oea t t olz t oez t oea t olz t oez t clz t oez t clz t olz t data out b data out b asc t remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
21 MC-428LFF721 hyper page mode (edo) early write cycle data in v ih v il v ih v il /we v ih v il address v ih v il v ih v il /ras crp t rad t asr t rah t asc t cah t asc t cah t wch t wcs t wch t dh t ds t ds t dh t data in data in ds t dh t wch t row col. col. col. asc t cah t cpn t rp t ral t hcas t cp t hcas t hpc t rsh t rhcp t rasp t cp t hcas t rcd t csh t wcs t wcs t /cas dq remarks 1. /oe : dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
22 MC-428LFF721 hyper page mode (edo) late write cycle /ras address /we col. col. col. row hi-z hi-z hi-z data in data in data in /oe rasp t rhcp t rp t cpn t rsh t hcas t hcas t hpc t cp t cp t csh t hcas t rcd t crp t asr t rah t rad t cah t cah t asc t ral t cah t wp t rwl t cwl t rcs t wp t cwl t wp t rcs t cwl t rcs t oeh t oeh t oeh t oed t ds t dh t oed t ds t dh t oed t ds t dh t v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il asc t asc t /cas dq remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
23 MC-428LFF721 hyper page mode (edo) read modify write cycle t rcs /cas t cpn t cp t hcas t hcas t cp t hprwc t hcas t rcd /ras t rasp t rp t crp address t asr t rah t rad t asc t cah t asc t cah t cah t asc row col. col. col. t ral /we t rwd t olz t dh t ds t awd t cwd t wp t rcs t cwl t acp t cpwd t awd t cwd t wp t cwl t acp t cpwd t awd t cwd t rcs t cwl t rwl t wp /oe dq out t clz t oed t oea t cac t aa t rac in t oea t oeh t cac t aa t olz t dh t ds out t oez t oed in t olz t dh t ds out t oez t clz t oed in t oeh t aa t cac t oea t oeh hi-z hi-z hi-z hi-z dq v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t oez t clz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
24 MC-428LFF721 hyper page mode (edo) read and write cycle t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t rad t cah t asc t cah t asc t cah t ral t rcs t rch t acp t aa t cac t wez t dhc t oea t rac t aa t cac t clz row col. col. col. data out data out hi - z t wcs t wch hi - z t dh t ds data in t och t olz cho t /ras v ih v il v ih v il address v ih v il /we v ih v il /oe v ih v il v oh v ol v ih v il t asc t oez /cas dq dq remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
25 MC-428LFF721 /cas before /ras refresh cycle t t t t t t t t t t t t t t t t csr chr wsr whr rc rp rpc csr chr ras ras rp rc rpc cpn crp /ras v ih v il v ih v il /we v ih v il t t wsr whr /cas /ras remark address, /oe : don't care dq : hi-z /ras only refresh cycle row row t rc t rc t ras t ras t rp t rp t crp t rpc t cpn t asr t asr t rah t rah t crp v ih v il /ras v ih v il v ih v il address /cas remark /we, /oe : don't care dq : hi-z
26 MC-428LFF721 hidden refresh cycle (read) tt t tt t row col. data out hi - z hi - z t t t t t t t t t t t t t t t t t t t t t t rc rc ras ras rp crp t rcd rsh chr cpn t asr rad rah ral cah asc rch whr wpz wez cho ofc ofr oez rcs t oes t oea rac aa cac olz clz /ras v ih v il v ih v il address v ih v il /we v ih v il /oe v ih v il v oh v ol rp t /cas dq
27 MC-428LFF721 hidden refresh cycle (write) t t t t t t t t t t row col. t t t t t t t t data in rc ras rp rc ras rcd rsh chr cpn cah asc rad rah asr crp wcs t wch ds dh /ras v ih v il v ih v il address v ih v il /we v ih v il v ih v il rp t /cas dq t whr t wsr remark /oe : dont care
28 MC-428LFF721 package drawings [ MC-428LFF721fh ] 168 pin dual in-line module (soket type) item millimeters inches a1 a c 36.83 1.450 u 4.00 min. 0.157 min. b 11.43 0.450 s t 1.270.1 0.0500.004 d1 6.35 0.250 d2 2.0 0.079 x 2.540.10 0.1000.004 133.35 5.250 133.350.13 5.2500.006 g 6.35 0.250 e 54.61 2.150 h 1.27 (t.p.) 0.050 (t.p.) i 8.89 0.350 3.125 0.123 j l 17.78 0.700 k 42.18 1.661 m 31.750.13 1.2500.006 m1 11.97 0.471 24.495 0.964 r 4.000.10 0.157 +0.005 C0.004 y 3.0 min. 0.118 min. f m168s-50a57 z 3.0 min. 0.118 min. m2 19.78 0.779 n 3.0 max. 0.119 max. v 0.25 max. 0.010 max. w 1.00.05 0.039 +0.003 C0.002 d 3.0 0.118 f p 1.0 0.039 q r2.0 r0.079 y r j h d q u t detail of a part d2 p x v a (optional holes) s w n z b i g detail of b part d1 m1 (area b) m2 (area a) l e a (area b) c b k a1 (area a) m h
29 MC-428LFF721 [ MC-428LFF721fb ] n t u m 168 pin dual in-line module (socket type) p d item millimeters inches u 4.0 min. 0.157 min. s t 1.270.1 0.050.004 a b 11.43 133.350.13 5.2500.006 0.450 c d 6.35 36.83 1.450 0.250 e g 6.35 54.61 2.150 0.250 h 1.27 (t.p.) 0.050 (t.p.) i 8.89 0.350 j 24.495 0.964 k 42.18 1.661 l 17.78 0.700 m n r 4.00.1 0.157 q v 0.25 max. 0.010 max. r2.0 r0.079 +0.005 C0.004 5.08 max. 0.200 max. 3.0 0.118 p 1.0 0.039 y 3.0 min. 0.118 min. w x 2.54 min. 1.00.05 0.1000.004 z 3.0 min. 0.118 min. 0.039 +0.003 C0.002 w g v x y r s l q z j h c b k g i b de a (optional holes) a detail of part detail of part 31.75 1.250 ub3js
30 MC-428LFF721 [memo]
31 MC-428LFF721 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme-diately after power-on for devices having reset function. notes for cmos devices
MC-428LFF721 [memo] caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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